AMPERE-developed Taskgraph framework enhances programmability and performance for rail and automotive industries
Success story: as Ampere project ends, the RESPECT project opens doors for next steps for critical embedded systems
AMPERE Project Showcases Fault-Tolerant Applications Through OpenMP at the 10th BSC Severo Ochoa Doctoral Symposium
AMPERE Project Showcases Real-time Scheduling and Power-aware Optimization Techniques at 5th OSPM Summit
With the finish line in sight, AMPERE project partners meet in Porto to discuss final months of the project
AMPERE Presents at HiPEAC 2023's Workshop on Adaptive CPSoS

Wrap-up of 2022
Publication notice: Heuristic-based Task-to-Thread Mapping in Multi-Core Processors
AMPERE at the Smart City Expo World Congress in Barcelona
Ampere's General Meeting in Barcelona
AMPERE researchers publish a new holistic framework to help with partition of real-time applications on heterogeneous platforms.
Software-based fault-tolerance for resilient parallel systems

From DSML to OpenMP: a multi-criteria automatic optimization
AMPERE 3rd General Assembly
Leveraging predictable FPGA-based hardware acceleration
'Women in STEM' interview featuring AMPERE scientist Delphine Longuet
Success story: AMPERE leverages OmpSs improvements developed in the LEGaTO project
AMPERE training at ACACES 2021
AMPERE training at Ada-Europe 2021
'Women in STEM' interview featuring AMPERE scientist Viola Sorrentino
Tackling mixed-criticality for automotive
1st 'Women in STEM' interview part of a series featuring AMPERE scientist Sara Royuela
ARTEMIS article about AMPERE as a CPS success story
AMPERE and Energy Efficiency in Model-Based Designed Cyber-Physical Systems
AMPERE's first video was released
AMPERE featured in Scientific Computing World
AMPERE 2nd General Assembly
AMPERE at the SoS integration with CPS workshop
AMPERE's advancements in 2020

AMPERE's Obstacle Detection and Avoidance System (ODAS) by the use of CAPELLA