AMPERE-developed Taskgraph framework enhances programmability and performance for rail and automotive industries

AMPERE-developed Taskgraph framework enhances programmability and performance for rail and automotive industries

Barcelona. 30 May 2023-- Members of the European-funded project, AMPERE have announced the development of a new OpenMP-compliant task-dependency graph-based framework, called Taskgraph, with implications for rail and automotive industries. This framework represents a potential breakthrough in the use of mainstream tasking approaches. The Taskgraph framework outperforms the standard vanilla OpenMP Task-based applications and increases performance in shared memory systems in High-Performance Computing (HPC). The framework targets programmability and performance while considering non-functional requirements derived from critical real-time systems like resilience and time predictability.

Sara Royuela, Established Researcher in the Predictable Parallel Computing Group of the Computer Sciences Department of the BSC believes that the Taskgraph framework, “represents a breakthrough for the OpenMP tasking model. It goes beyond reducing current overheads that limit the use of OpenMP tasks for the implementation of HPC systems. It is a big step towards the use of OpenMP for the implementation of safety-critical real-time embedded systems by enabling timing and functional analysis techniques”.

OpenMP is recognised as the de-facto standard for shared memory systems in High-Performance Computing because it includes a task-based model with a high-level of abstraction. However, the run-time overheads in most common OpenMP frameworks are high, making it primarily suitable for coarse-grained tasks. The framework, presented in the paper, “Taskgraph: A Low Contention OpenMP Tasking Framework”, uses a task dependency graph to reduce the run-time overheads associated with task management, making it suitable for both coarse- and fine- grained tasks. 

The proposed framework allows OpenMP Task-based applications to reach levels of performance that are comparable to traditional thread-based parallel applications. It also reduces the performance gap between the task and the thread models of OpenMP.

Key benefits of the Taskgraph framework include:

  • avoiding the overheads related to the resolution of task dependencies and greatly reducing those deriving from the access to shared resources
  • introducing the record-and-replay execution model into OpenMP, which accelerates the Taskgraph region from its second execution
  • exploiting fine-grained OpenMP tasks to cope with the trend in current applications that leverage massive on-node parallelism, fine-grained and dynamic scheduling paradigms

An OpenMP framework overview

Overview frameworks

Figure 1: OpenMP frameworks overview: Taskgraph (above) and vanilla (below).


One more step for AMPERE Technology

The Taskgraph framework represents a core piece of the AMPERE software development ecosystem, as it allows for an automatic translation of AMALTHEA models into parallel OpenMP code exploiting intra-process parallelism. It thus bridges the gap between the multi-process, single-threaded execution that is currently described by state-of-the-art model-Domain Specific Modeling Languages (DSML) for complex Cyber-Physical Systems (CPS), like in the AMPERE use-cases. It also enables seamless communication between the different multi-criteria optimization tools to ensure timing and energy budgets, while considering resilience and performance. This is required for exploiting model parallel and heterogeneous processor architectures used in the targeted CPS.


The European funded project AMPERE is a Research and Innovation Action (RIA) project, which kicked off on 1 January 2020 and will end on 30 June 2023. It benefits from a €4.9 million budget, fully funded by the European Union (EU). To reach its goals, AMPERE brings together nine EU partners: BSC (Spain) as coordinator, ISEP (Portugal), ETH Zürich (Switzerland), SSSA (Italy), EVI (Italy), BOSCH (Germany), THALES (France), THALIT (Italy) and SYSGO (Czech Republic). These leading academic institutions and industrial partners will provide the required expertise to develop the novel framework and application of the use cases.

Further information

Janine Gehrig Lux, Senior Science Dissemination Officer, Barcelona Supercomputing Center

Email:, Tel: +34 93 401 5742


The PDF version of the press release can be found here.