AMPERE's run-time software architecture

AMPERE's run-time software architecture

The AMPERE consortium has been working on a first sketch of the run-time software architecture that is foreseen to be realized throughout the project. The picture below represents a comprehensive view of the full software stack that will be supporting the AMPERE use-case applications at run-time, which span across the automotive and railway domains.

 

Possible instance of the AMPERE run-time architecture.
Possible instance of the AMPERE run-time architecture.

 

On the bottom, we can see one of the reference hardware platforms that have been chosen throughout the project for our future activities, a Xilinx UltraScale+ board. This is a challenging heterogeneous platform that includes many of the key characteristics that are central to the research planned throughout the AMPERE project, including the presence of: different multi-core islands, with the Cortex-A one specializing on general-purpose computing and the Cortex-R one on real-time computing; a GPU device for accelerating graphics applications; a dynamically reprogrammable FPGA fabric where it is possible to deploy dynamically at run-time both hardware accelerator and additional CPU soft-cores, as needed; and advanced energy management and control capabilities.

These hardware capabilities will be managed throughout a software stack that includes: a real-time hypervisor like PikeOS, which is capable of providing partitioning and strong isolation among higher layer components deployed as individual “personalities”. This makes possible the coexistence on the same board of a hard real-time software stack like the Erika Enterprise OS, and at the same time a soft real-time OS like Linux.

In both domains, various adaptations of the OS kernel and capabilities are planned to be realized by partners of the AMPERE consortium, in order to provide the key capabilities that are needed in order to support at run-time the planned real-time use-cases, in an energy-efficient way. In particular, specific features will be needed to orchestrate the execution of complex real-time applications making use of GPU/FPGA acceleration, and at the same time fine-tune the energy configuration and set-up of the platform, depending on the real-time workload that is deployed and activated on the board at any time. Key capabilities of the run-time architecture will include the support for a parallel programming model like OpenMP, as well as middleware for real-time component-based applications and real-time communications, like the AUTOSAR run-time environment (RTE), ROS2 and DDS.

To let these applications run respecting their end-to-end deadline constraints, it is important to deploy advanced real-time scheduling techniques where the scheduling parameters to be used, as well as the tunables available on the board for power consumption control, need to be accurately chosen as a result of an overall platform optimization and advanced schedulability analysis techniques ensuring no deadline misses will be able to occur at run-time.

For what concerns the soft real-time domain, a particularly challenging task for the run-time architecture will be the one to estimate and/or refine the power consumption profile of the individual applications at run-time, which is foreseen to be made possible through the adoption of a power consumption model to be tuned via off-line profiling based on a number of benchmarks.