Leveraging predictable FPGA-based hardware acceleration
Contemporary heterogeneous computing platforms are an essential tool to meet the increasing computational demand required by modern cyber-physical systems. In particular, SoC-FPGA platforms are particularly suitable for safety-critical embedded systems due to the highly predictable nature of FPGA-based hardware acceleration. Moreover, dynamic partial reconfiguration can significantly improve resources utilization by allowing logic resources to be shared between multiple hardware accelerators. The FRED framework [1] has been developed as a solution to leverage FPGA-based reconfigurable hardware acceleration while preserving the predictability required by real-time systems.
FRED contributes to tackling the challenges addressed in the AMPERE project by providing a device model and a scheduling infrastructure designed to guarantee bounded response times. This characteristic is crucial for making dynamic hardware acceleration viable for safety-critical applications. The scheduling infrastructure is in charge of managing concurrent acceleration requests performed by software activities.
A novel version of Fred-Linux [2], an implementation of the FRED framework for GNU/Linux, has been developed in the context of the AMPERE project. The new version presents many improvements over the initial release. In particular, the core software component of Fred-Linux has been entirely redesigned from scratch in a more modular fashion to improve support for future extensions of the framework. Moreover, the new implementation supports new features such as asynchronous acceleration requests and watchdog timers for detecting Hw-tasks stalls. Finally, the device reconfiguration is now managed by a low-level driver based on the Linux vendor-independent FPGA manager framework. With this new reconfiguration driver, Fred-Linux now fully supports both Zynq-7000 and Zynq UltraScale+ platforms by Xilinx. This novel version of the Fred-Linux runtime will be integrated into the AMPERE project software ecosystem, providing FPGA-based reconfigurable hardware acceleration in a predictable fashion.
[1] A. Biondi, A. Balsini, M. Pagani, E. Rossi, M. Marinoni, and G. Buttazzo, “A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs”, Proc. of the IEEE Real-Time Systems Symposium (RTSS 2016), Porto, Portugal, Nov. 29 - Dec. 2, 2016.
[2] M. Pagani, A. Balsini, A. Biondi, M. Marinoni, and G. Buttazzo, “A Linux-based Support for Developing Real-Time Applications on Heterogeneous Platforms with Dynamic FPGA Reconfiguration”, Proc. of the 30th IEEE Int. System-on-Chip Conference (SOCC 2017), Munich, Germany, September 5-8, 2017.